The present invention relates to a dynamic type semiconductor memory device and, more particularly, to a dynamic type semiconductor memory device manufactured with a very high integration density.
The improvement of the recent dynamic type semiconductor memory device is remarkable in integration density. In a general dynamic type semiconductor memory device, memory cells are arranged on a semiconductor memory chip in a matrix array. Data is read out of and written into memory cells through bit lines. Word lines each supply to the memory cells an enable signal to permit the read and write operations of data. A known memory cell 10 shown in FIG. 1 includes a capacitor 12 for storing an amount of charge corresponding to data, i.e. binary "1" or "0", and a transfer gate for controlling the charging and discharging to and from the capacitor 12. The transfer gate is formed of an enhancement type n-channel MOS transistor 14. A word line 16 is connected to the gate of the MOS transistor 14, while a bit line 18 is connected to the capacitor 10 via a current path of the MOS transistor 14.
For writing data into the memory cell 10, a high level voltage, e.g. +5 V, as shown in FIG. 2, is supplied to the word line 16 in order to turn on the MOS transistor 14. During a period that the MOS transistor 14 is conductive, an amount of charge corresponding to data is stored in the capacitor 12 through the bit line 18. After charging and discharging to and from the capacitor 12, the word line 16 is supplied with a low level voltage, i.e. 0 V as shown in FIG. 2, in order to turn off the MOS transistor 14.
For reading out data, charge stored in the capacitor 12 is transferred to the bit line 18 during a period that the MOS transistor 14 is conductive.
In manufacturing the dynamic memory of 1 M bits, for example, the MOS transistors in the memory cells must be designed to be extremely short in channel length. If so designed, the charges stored in the capacitor 12 are easy to move out of the capacitor even if the MOS transistor 14 is in an off state. Therefore, it is very difficult for the memory cell to hold data for a long time. This indicates that, in the dynamic type semiconductor memory device with such a structure, the refreshing interval for the memory cells must be shorter, as an integration density of the memory device is improved. Conversely, if the refreshing interval is fixed, the memory device is greatly restricted in increasing the integration density.